Positron AI raises $875M at $5B valuation for Asimov ASIC using LPDDR5X instead of HBM, betting >90% utilization beats HBM's raw bandwidth in inference decode
September 12, 2026
brightray analysis
Summary
Positron AI closed an $875M Series C at a $5B valuation to fund Asimov, a custom inference ASIC on TSMC N3P using LPDDR5X commodity memory rather than HBM. The core architectural claim: GPU inference achieves <30% of available HBM bandwidth during sequential token decode, while Asimov targets >90% utilization of its LPDDR5X bandwidth — making effective throughput competitive despite lower peak specs. All Asimov performance figures are design targets; the chip has not yet taped out, and independent third-party verification of Atlas (the current shipping product) has not been completed.
Why it matters
- Positron claims inference chips achieve <30% HBM bandwidth utilization during decode, and Asimov's memory-first design targets >90% — if verified, this would make LPDDR5X competitive with HBM in practice despite lower peak specs
- HBM supply constraints have already forced Nvidia to scale Rubin Ultra from 1TB to ~192GB HBM4E; LPDDR5X has no equivalent supply bottleneck and is available from SK Hynix, Samsung, and Micron at commodity scale
- Gartner data confirms inference spending surpassed training for the first time in 2026 ($23.3B vs $19B), and a concurrent Qualcomm/AWS $60B LPDDR inference deal independently validates the architectural thesis
- Asimov supports up to 2.3TB of memory per chip via CXL expansion — vs 80-288GB for current Nvidia GPUs — and Titan targets air-cooled operation, enabling facilities that cannot support liquid-cooled GPU clusters
- All Asimov specs are design targets, not silicon results; tapeout is late 2026 and production is H2 2027, so enterprise buyers cannot validate claims until production samples are available
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